Tileable field-programmable gate array architecture

ABSTRACT

An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent applicationSer. No. 11/561,705, filed Nov. 20, 2006, which is a continuation ofU.S. patent application Ser. No. 11/335,396, filed Jan. 18, 2006, nowissued as U.S. Pat. No. 7,157,938, which is a continuation of U.S.patent application Ser. No. 11/056,957, filed Feb. 11, 2005, now issuedas U.S. Pat. No. 7,015,719, which is a continuation of U.S. patentapplication Ser. No. 10/429,002, filed Apr. 30, 2003, now issued as U.S.Pat. No. 6,888,375, which is a continuation of U.S. patent applicationSer. No. 10/066,398, filed Jan. 30, 2002, now issued as U.S. Pat. No.6,700,404, which is a continuation-in-part of U.S. patent applicationSer. No. 09/654,240, filed Sep. 2, 2000, now issued as U.S. Pat. No.6,476,636, which are hereby incorporated by reference as if set forthherein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to field-programmable gate arrays, andmore particularly, to architecture for tileable field-programmable gatearrays.

2. Description of the Related Art

A field-programmable gate array (FPGA) is an integrated circuit (IC)that includes a two-dimensional array of general-purpose logic circuits,called cells or logic blocks, whose functions are programmable. Thecells are linked to one another by programmable buses. The cell typesmay be small multifunction circuits (or configurable functional blocksor groups) capable of realizing all Boolean functions of a fewvariables. The cell types are not restricted to gates. For example,configurable functional groups typically include memory cells andconnection transistors that may be used to configure logic functionssuch as addition, subtraction, etc., inside of the FPGA. A cell may alsocontain one or two flip-flops. Two types of logic cells found in FPGAsare those based on multiplexers and those based on programmable readonly memory (PROM) table-lookup memories. Erasable FPGAs can bereprogrammed many times. This technology is especially convenient whendeveloping and debugging a prototype design for a new product and forsmall-scale manufacture.

FPGAs typically include a physical template that includes an array ofcircuits, sets of uncommitted routing interconnects, and sets of userprogrammable switches associated with both the circuits and the routinginterconnects. When these switches are properly programmed (set to on oroff states), the template or the underlying circuit and interconnect ofthe FPGA is customized or configured to perform specific customizedfunctions. By reprogramming the on-off states of these switches, an FPGAcan perform many different functions. Once a specific configuration ofan FPGA has been decided upon, it can be configured to perform that onespecific function.

The user programmable switches in an FPGA can be implemented in varioustechnologies, such as ONO antifuse, M-M antifuse, SRAM memory cell,Flash EPROM memory cell, and EEPROM memory cell. FPGAs that employ fusesor antifuses as switches can be programmed only once. A memory cellcontrolled switch implementation of an FPGA can be reprogrammedrepeatedly. In this scenario, an NMOS transistor is typically used asthe switch to either connect or disconnect two selected points (A, B) inthe circuit. The NMOS' source and drain nodes are connected to points A,B respectively, and its gate node is directly or indirectly connected tothe memory cell. By setting the state of the memory cell to eitherlogical “1” or “0”, the switch can be turned on or off and thus point Aand B are either connected or disconnected. Thus, the ability to programthese switches provides for a very flexible device.

FPGAs can store the program that determines the circuit to beimplemented in a RAM or PROM on the FPGA chip. The pattern of the datain this configuration memory CM determines the cells' functions andtheir interconnection wiring. Each bit of CM controls a transistorswitch in the target circuit that can select some cell function or make(or break) some connection. By replacing the contents of CM, designerscan make design changes or correct design errors. The CM can bedownloaded from an external source or stored on-chip. This type of FPGAcan be reprogrammed repeatedly, which significantly reduces developmentand manufacturing costs.

In general, an FPGA is one type of programmable logic device (PLD),i.e., a device that contains many gates or other general-purpose cellswhose interconnections can be configured or “programmed” to implementany desired combinational or sequential function. As its name implies,an FPGA is “field-programmable”, meaning that the device is generallyprogrammed by designers or end users “in the field” via small, low-costprogramming units. This is in contrast to mask programmable deviceswhich require special steps in the IC chip-manufacturing process.

A field-programming unit typically uses design software to program theFPGA. The design software compiles a specific user design, i.e., aspecific configuration of the programmable switches desired by theend-user, into FPGA configuration data. The design software assemblesthe configuration data into a bit stream, i.e., a stream of ones andzeros, that is fed into the FPGA and used to program the configurationmemories for the programmable switches. The bit stream creates thepattern of the data in the configuration memory CM that determineswhether each memory cell stores a “1” or a “0”. The stored bit in eachCM controls whether its associated transistor switch is turned on oroff. End users typically use design software to test different designsand run simulations for FPGAs.

When an FPGA that has been programmed to perform one specific functionis compared to an application specific integrated circuit (ASIC) thathas been designed and manufactured to perform that same specificfunction, the FPGA will necessarily be a larger device than the ASIC.This is because FPGAs are very flexible devices that are capable ofimplementing many different functions, and as such, they include a largeamount of excess circuitry that is either not used or could be replacedwith hard-wired connections when performing one specific function. Suchexcess circuitry generally includes the numerous programmable transistorswitches and corresponding memory cells that are not used inimplementing the one specific function, the memory cells inside offunctional groups, and the FPGA programming circuitry. This excesscircuitry is typically eliminated in the design of an ASIC, which makesthe ASIC a smaller device. An ASIC, on the other hand, is not a flexibledevice. In other words, once an ASIC has been designed and manufacturedit cannot be reconfigured to perform a different function like ispossible with an FPGA.

Designers of FPGAs (as well as other PLDs) often provide their circuitdesigns to IC manufacturers who typically manufacture the FPGAs in twodifferent ways. First, an FPGA design may be manufactured as its ownchip with no other devices being included in the IC package. Second, anFPGA design may be embedded into a larger IC. An example of such alarger IC is a system on a chip (SOC) that includes the embedded FPGA aswell as several other components. The several other components mayinclude, for example, a microprocessor, memory, arithmetic logic unit(ALU), state machine, etc. In this scenario the embedded FPGA may beonly a small part of the whole SOC.

Whether an FPGA is to be manufactured as its own IC or embedded into alarger IC (e.g., an SOC), the intended application/use of the IC willdetermine the size and complexity of the FPGA that is needed. In somescenarios a large FPGA is needed, and in other scenarios a small FPGA isneeded. Because conventional FPGAs are typically designed for theirintended application/use, an FPGA designed to fulfill a need for a smallFPGA must be substantially redesigned for use where a larger FPGA isneeded. Therefore, it would be highly advantageous to have an FPGAapparatus and method that could be easily adapted for use in both ICsrequiring large FPGAs and ICs requiring small FPGAs. Furthermore, itwould be highly advantageous if such FPGA apparatus and method could beused in both the scenario where the FPGA is to be manufactured as itsown IC and the scenario where the FPGA is to be embedded into a largerIC.

BRIEF SUMMARY OF THE INVENTION

The present invention provides an apparatus that includes afield-programmable gate array (FPGA). The FPGA includes a first FPGAtile, and the first FPGA tile includes a plurality of functional groups(FGs), a first set of routing conductors, and a plurality of interfacegroups (IGs). The plurality of FGs are arranged in rows and columns witheach of the FGs coupled to the first set of routing conductors toreceive input signals, perform a logic operation, and generate signalsthrough first outputs coupled to said first set of routing conductors.The first set of routing conductors is coupled to the FGs and configuredto receive signals, route signals within the first FPGA tile, andprovide the signals to the FGs via first input ports. The plurality ofIGs surround the plurality of FGs such that one IG is positioned at eachend of each row and column. Each of the IGs is coupled to the first setof routing conductors and configured to transfer signals from the firstset of routing conductors to outside of the first FPGA tile.

A better understanding of the features and advantages of the presentinvention will be obtained by reference to the following detaileddescription of the invention and accompanying drawings, which set forthan illustrative embodiment in which the principles of the invention areutilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an FPGA tile in accordance withthe present invention.

FIGS. 2, 3A, 3B and 4 are block diagrams illustrating variousconfigurations of FPGA tiles in accordance with the present invention.

FIG. 5 is a block diagram illustrating in further detail the FPGA tileshown in FIG. 1.

FIG. 6 is a block diagram illustrating in further detail one of thefunctional groups (FGs) shown in FIG. 5.

FIG. 7 is a schematic diagram illustrating in further detail the FGshown in FIG. 6.

FIG. 8 is a schematic diagram illustrating in further detail the LGGselection circuit shown in FIG. 7.

FIG. 9 is a schematic diagram illustrating in further detail the C/E/P/Cselection circuit shown in FIG. 7.

FIG. 10 is a schematic diagram illustrating in further detail one of thelogic units (LU) shown in FIG. 7.

FIG. 11 is a block diagram illustrating in further detail one of theinterface groups (IGs) shown in FIG. 5.

FIG. 12 is a block diagram illustrating in further detail an alternativeversion of one of the interface groups (IGs) shown in FIG. 5.

FIG. 13 is a schematic diagram illustrating in further detail a portionof the FPGA tile shown in FIG. 5.

FIG. 14 is a schematic diagram illustrating in further detail a portionof the regular routing structure shown in FIG. 13.

FIG. 15 is a schematic diagram illustrating in further detail a portionof the first set of routing conductors as shown in FIG. 14.

FIGS. 16A and 16B are schematic diagrams illustrating the second set ofrouting conductors included in the FPGA tile shown in FIG. 5.

FIG. 17 is a schematic diagram illustrating in further detail the globalrouting structure shown in FIG. 4.

FIG. 18 is a schematic diagram illustrating an optional method ofcoupling two FPGA tiles together.

FIG. 19 is a schematic diagram illustrating the input and output portsof the second set of routing conductors included on the FPGA tile shownin FIG. 5.

FIG. 20 is a schematic diagram illustrating the input and output portsof the third set of routing conductors shown in FIG. 5

FIG. 21 is a schematic diagram illustrating in further detail a portionof the third set of routing conductors shown in FIG. 20.

FIG. 22 is a schematic diagram illustrating in further detail a portionof the third set of routing conductors between top/bottom interfacegroups (IGs).

FIG. 23 is a schematic diagram illustrating in further detail a portionof the third set of routing conductors between left/right interfacegroups (IGs).

FIG. 24 is a flowchart illustrating a method of routing the FPGA tileshown in FIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, there is illustrated a field-programmable gatearray (FPGA) tile 20 in accordance with the present invention. The FPGAtile 20 overcomes many of the disadvantages of conventional FPGAs inthat it can be easily adapted for use in both integrated circuits (ICs)requiring large FPGAs and ICs requiring small FPGAs. Furthermore, theFPGA tile 20 can be used where the FPGA is to be manufactured as its ownIC and where the FPGA is to be embedded into a larger IC (e.g., a systemon a chip (SOC)).

One feature of the FPGA tile 20 that makes it such a flexible andadaptable device is that it is “tileable”. As used herein, the term“tileable” means that the FPGA tile 20 can be combined with other FPGAtiles to form a larger FPGA. For example, FIG. 2 illustrates an FPGA 22that is formed by combining two FPGA tiles 20. The two FPGA tiles 20work together and communicate with each other to form the larger FPGA22. It should be well understood that any number of FPGA tiles 20 may becombined in accordance with the present invention to form a larger FPGA.For example, FIG. 3A illustrates an FPGA 24 that is formed by combiningfour FPGA tiles 20.

In accordance with the present invention, FPGA tiles 20 may be combinedto form a larger FPGA that is to be manufactured as its own IC or thatis to be embedded into a larger IC. For example, with respect to thelater scenario, the FPGAs 22, 24 may be embedded into SOCs. FIG. 3Bshows an SOC 25 having the FPGA 24 embedded therein. The SOC 25 includesseveral other components. The other components may include, for example,a read only memory (ROM) 27, a random access memory (RAM) 29, amicroprocessor 31, and any other components 33. It should be wellunderstood that the specific types of other components and the number ofother components included on the SOC 25 will vary greatly depending onthe particular application. With respect to the former scenario, FIG. 4illustrates an FPGA 26 that has been manufactured as its own IC.Specifically, the FPGA 26 includes four FPGA tiles 20 and four pad rings28, 30, 32, 34. The pad rings 28, 30, 32, 34 are used to couple the FPGAtiles 20 to the IC package pins of the FPGA 26.

Also illustrated in FIG. 4 is a global routing structure 36. The globalrouting structure 36 will be described in more detail below, but ingeneral, it is a routing structure used to route inter-tile globalsignals between the FPGA tiles 20. It should be understood that theglobal routing structure 36 may be included in any combination of FPGAtiles 20, including for example the FPGAs 22, 24, in accordance with thepresent invention. Furthermore, the global routing structure 36 may beused whether the combined FPGA tiles 20 are manufactured as their own ICor embedded into a larger IC.

The FPGA tiles that are combined may be identical (as are the tiles inthe FPGAs 22, 24, 26), or of different sizes and designs in accordancewith the present invention. An advantage of using identical FPGA tilesis that it provides an economical solution for providing FPGAs havingsizes that are appropriate for the intended uses/applications. Such asolution is economical because only one FPGA tile needs to be designed,and then the necessary number of tiles are combined to form an FPGA.Additionally, it should be understood that an “FPGA tile” is consideredherein to be an FPGA. In other words, a single FPGA tile 20 can be usedby itself to form an FPGA.

Referring to FIG. 5, there is illustrated some of the internalcomponents of the FPGA tile 20. Specifically, the FPGA tile 20 includesseveral functional groups (FGs) 40 that are surrounded by severalinterface groups (IGs) 42. The FGs 40 are small multifunction circuitsthat are capable of realizing many or all Boolean functions. The FGs 40include look-up tables (LUTs) and other circuits capable of realizingBoolean functions, as well as memory cells that are used to configurelogic functions such as addition, subtraction, etc. The IGs 42 are usedfor interfacing the FPGA tile 20 to other FPGA tiles or devices, or topad rings for connecting the FPGA tile 20 to IC package pins. Ingeneral, the logic structure of the FPGA tile 20 is provided by the FGs40 and the IGs 42. Also included in the FPGA tile 20, but not shown inFIG. 5, are several horizontal and vertical regular routing buses,routing interconnect areas, switching transistors, and global routingstructure, all of which will be discussed below.

Referring to FIG. 6, an exemplary version of the FG 40 includes firstset of input and output ports 44, intra-tile global input and outputports 46, and inter-tile global input port 48. The first set of inputand output ports carry input signals EUI[0:4] (upper input) and EBI[0:4](bottom input). These inputs are the basic inputs on which the Booleanfunctions and logic operation of the FG 40 are performed. The first setof input and output ports 44 also carry output signals Y[0:4]. Thesesignals are the basic outputs, which carry the result of the Booleanfunctions and logic operation of the FG 40. The first set of input andoutput ports 44 route signals that are carried within the FPGA tile 20on horizontal and vertical regular routing buses and routinginterconnect areas. If any of the signals sent via first inputs andoutput ports 44 are to be sent to a different FPGA tile, they are passedthrough an IG 42 as shown in FIG. 5.

The intra-tile global input and output ports 46 carry input signalsLGG[0:5] and output signal LINT. The LINT signal is carried via a secondset of routing resources. Specifically, in some situations the first setof routing output signals Y[0:4] cannot be sent to the intended FG 40because the first set of routing conductors and routing interconnectareas do not provide the necessary connections. Or, in other situations,it may be desirable not to use the system central processing unit (CPU)time to send a signal through the first set of routing conductors androuting interconnect areas. In these situations, the needed one of theregular routing output signals Y[0:4] can be selected as the LINTsignal. The LINT signal is routed around the FPGA tile 20 by a routingstructure that is separate from the first set of routing conductors androuting interconnect areas used to route the first set of output signalsY[0:4]. Therefore, the LINT signal can be sent to any FG 40 or IG 42regardless of whether the first set of routing conductors and routinginterconnect areas provide the necessary connections. The LINT signalsare received by the FG 40 via input ports LGG[0:5] which are part of thesecond set of routing conductors carrying the LINT signals. As its nameimplies, the intra-tile global input and output ports 46 carry signalsthat are routed within the boundaries of the FPGA tile 20 and arepreferably not routed between FPGA tiles. The intra-tile global inputsand output ports 46 and the generation and use of the LINT signal willbe discussed in more detail below.

The inter-tile global input port 48 carries the input signals GG[0:7].These signals are sent to every FG 40 in all FPGA tiles. As will bediscussed below, selected ones of the input signals GG[0:7] are used tocontrol the clock/enable/preset/clear (C/E/P/C) inputs of flip-flopsincluded in each FG 40.

Each FG 40 also includes a CL input and a CO output. The purpose ofthese input and output ports is to implement a carry chain for fasterutilization of logic resources.

Referring to FIG. 7, each FG 40 preferably includes four logic units(LU) 50, 52, 54, 56. The LUs 50, 52, 54, 56 provide the Booleanfunctions and logic operations of the FG 40. Each of the LUs 50, 52, 54,56 includes several inputs on which Boolean functions and logicoperations are performed. As shown, each of the LUs 50, 52, 54, 56includes twenty such inputs, but it should be understood that the numberof inputs may vary in accordance with the present invention.Specifically, each of the LUs 50, 52, 54, 56 receives signals throughinput ports UI[0:4] and BI[0:4] which correspond to signals receivedthrough regular input ports EUI[0:4] and EBI[0:4] discussed above.Furthermore, each of the LUs 50, 52, 54, 56 receives signals throughinput port GI[0:1]. The input signals GI[0:1] are generated by the LGGselection circuit 58 which selects two of the input signals LGG[0:5]. Asmentioned above, the input port LGG[0:5] carries selected ones of thesignals traveling via the LINT bus. Finally, each of the LUs 50, 52, 54,56 receives signals via input port JI[0:7]. The input signals via inputport JI[0:7] include two output signals from each of the LUs 50, 52, 54,56. Thus, two output signals of each of the LUs 50, 52, 54, 56 are fedback to the inputs by way of JI[0:7].

Each of the LUs 50, 52, 54, 56 also includes a clock/enable/preset/clear(C/E/P/C) input. This input is used to control a flip-flop includedinside each of the LUs 50, 52, 54, 56. The C/E/P/C input is generated bya C/E/P/C selection circuit 60. The C/E/P/C selection circuit 60receives inputs EUI[0:4], EBI[0:4], JI[0:7], GI[0:1], and GG[0:7]. Fromthese signals, the C/E/P/C selection circuit 60 selects four signals tobe used as the C/E/P/C signals.

Each of the LUs 50, 52, 54, 56 includes three outputs: Y, JPO, and JO.These outputs carry the result of the Boolean functions and logicoperations performed by the LU. As already mentioned, the JPO and JOoutputs from each of the LUs 50, 52, 54, 56 are grouped together to formthe JI[0:7] bus which is fed back into the inputs of the LUs 50, 52, 54,56. The Y output from each of the LUs 50, 52, 54, 56 are groupedtogether to form Y[0:3] of the Y[0:4] bus. The Y[4] signal is selectedusing a multiplexer (or selection circuit) 62 to select from the JI[0:7]bus. An advantage of selecting the Y[4] signal from the JI[0:7] bus isthat it adds flexibility to the device. In other words, the JO or JPOoutput of any of the LUs 50, 52, 54, 56 can be chosen as the Y[4]signal.

The LINT signal can be selected to be any one of the Y[0:4] signalsusing a multiplexer 64. The use of the LINT signal adds a tremendousamount of flexibility to the FPGA tile 20 because the LINT signal can besent to any of the FGs 40 or IGs 42. This is because the LINT signal isrouted around the FPGA tile 20 using a routing structure that isseparate and independent from that of the Y[0:4] bus. In thosesituations where one of the signals on the Y[0:4] bus cannot be sent tothe desired destination or CPU time needs to be conserved, themultiplexer 64 can be used to select that one of the Y[0:4] signals asthe LINT signal in order to send the signal to the desired destination.

Referring to FIG. 8, one exemplary version of the LGG selection circuit58 includes two six-to-one multiplexers 66, 68. Each multiplexer 66, 68selects one of the input signals LGG[0:5]. The signal selected bymultiplexer 66 becomes the signal GI[0], and the signal selected bymultiplexer 68 becomes the signal GI[1]. Because the LGG[0:5] bus issupplied to both multiplexers 66, 68, it is possible for the signalsGI[0] and GI[1] to be the same signal. As mentioned above, the LGG[0:5]bus is a way for LINT signals from any FG 40 or IG 42 to be sent to anyFG 40 or IG 42. The exemplary version of the LGG selection circuit 58shown can select any two of these LINT signals for sending to the LUs50, 52, 54, 56 via the GI[0:1] bus. It should be understood, however,that various different designs of the LGG selection circuit 58 may beused to select various different numbers of signals from the LGG[0:5]bus for the LUs 50, 52, 54, 56 in accordance with the present invention.

Referring to FIG. 9, there is illustrated an exemplary version of theC/E/P/C selection circuit 60. The circuit 60 includes two twenty-to-onemultiplexers 70, 72. Each multiplexer 70, 72 selects one signal from thebuses EUI[0:4], EBI[0:4], JI[0:7], and GI[0:1]. The signal selected bymultiplexer 70 becomes the signal GX[0], and the signal selected bymultiplexer 72 becomes the signal GX[1]. The bus GX[0:1] is supplied tothe inputs of four eleven-to-one multiplexers 74, 76, 78, 80. Alsosupplied to the inputs of the four multiplexers 74, 76, 78, 80 are theGG[0:7] bus and a ground signal bus. The signal selected by multiplexer74 becomes the clock signal CLK, the signal selected by multiplexer 76becomes the enable signal E, the signal selected by multiplexer 78becomes the preset signal PRSTN, and the signal selected by multiplexer80 becomes the clear signal CLRN. The use of the four multiplexers 74,76, 78, 80 allows any of the signals GX[0:1], GG[0:7], and ground to beselected as one of the C/E/P/C signals.

As discussed above, the GG[0:7] bus is an inter-tile global bus that issent to every FG 40 in all FPGA tiles. The signals in the GG[0:7] busare often selected as the C/E/P/C signals. In addition, the C/E/P/Cselection circuit 60 advantageously allows the two signals GX[0:1] to beselected as the C/E/P/C signals. And the two signals GX[0:1] can beselected from any of the buses EUI[0:4], EBI[0:4], JI[0:7], and GI[0:1].Therefore, the C/E/P/C selection circuit 60 allows numerous differentsignals to be selected as the C/E/P/C signals, which provides for a veryflexible device. It should be well understood, however, that theillustrated C/E/P/C selection circuit 60 is just one exemplary versionof such a selection circuit and that various different designs of theC/E/P/C selection circuit 60 may be used to select various differentsignals in accordance with the present invention.

Referring to FIG. 10, there is illustrated an exemplary version of theLU 50. The LUs 50, 52, 54, 56 are preferably all of the same design, butit should be understood that such is not required in accordance with thepresent invention. The LU 50 includes two look-up tables (LUT) 82, 84.Each LUT 82, 84 includes three inputs A, B, C, an output Y, and severalinternal memory cells (not shown). The LUTs 82, 84 are configured byprogramming the internal memory cells, and the specific setting of theinternal memory cells taken together provides a specific configurationfor each of the LUTs 82, 84. The configuration data used to program theinternal memory cells is generated by design software. Once a specificconfiguration of the internal memory cells is decided upon, the inputsA, B, C may be used to generate the output Y in accordance with thedesired logic function.

The inputs A, B, C of the LUT 82 are provided by the twenty-to-onemultiplexers 86, 88, 90, respectively, and the inputs A, B, C of the LUT84 are provided by the twenty-to-one multiplexers 92, 94, 96,respectively. Each of the multiplexers 86, 88, 90, 92, 94, 96 receivesas inputs the four buses EUI[0:4], EBI[0:4], JI[0:7], and GI[0:1].Therefore, three signals are selected from these twenty signals as theinputs A, B, C for each of the LUTs 82, 84.

When only a three input LUT is needed, the LUT 82 can be used by itselfand the LUT 84 is not needed. The Y output of the LUT 82 can be sentdirectly to the JO output of the LU 50, or the Y output of the LUT 82can be sent to the Y output of the LU 50 by using the two-to-onemultiplexer 104 to select the Y output of the LUT 82. Additionally, theY output of the LUT 82 can be sent to the JPO output of the LU 50 byusing the two-to-one multiplexer 98 to select the Y output of the LUT 82and the two-to-one multiplexer 102 to select the output of themultiplexer 98. Thus, the multiplexers 98, 102, 104 can be used to sendthe Y output of the LUT 82 to any of the outputs Y, JO, JPO of the LU50.

One purpose of including two LUTs 82, 84 in the LU 50 is so that theycan be used together to provide a four-input LUT. Specifically, the Youtput of the LUT 82 and the Y output of the LUT 84 are connected to theinputs of the two-to-one multiplexer 98. The multiplexer 98 iscontrolled by the twenty-to-one multiplexer 100 which receives as itsinputs the four buses EUI[0:4], EBI[0:4], JI[0:7], and GI[0:1]. The LUTs82, 84 both receive the first, second and third inputs at their A, B, Cinputs, and the multiplexer 100 is programmed to select the fourth inputand provide it to the control input of the multiplexer 98. According towell-known Boolean logic techniques and the Shannon Expansion,connecting the three-input LUTs 82, 84 in this manner will simulate asingle four-input LUT with the result being generated at the output ofthe multiplexer 98. The output of the multiplexer 98 can be provided tothe JPO output of the LU 50 by way of the multiplexer 102 or to the Youtput of the LU 50 by way of the multiplexers 102, 104.

A flip-flop 106 is preferably also included in the LU 50. Specifically,the D input of the flip-flop 106 is connected to the output of themultiplexer 98, and the Q output of the flip-flop 106 is connected toone of the inputs of the multiplexer 102. The clock, enable, set andreset inputs of the flip-flop 106 are connected to the correspondingsignals of the C/E/P/C bus. One purpose of the flip-flop 106 is to storethe output data of the multiplexer 98. This data can be stored and latersent to the JPO output of the LU 50 by selecting the Q output with themultiplexer 102. The stored data can also be sent to the Y output of theLU 50 by selecting the JPO signal with the multiplexer 104. Theinclusion of the flip-flop 106 in the LU 50 adds to the flexibility ofthe device in that output data of the LU 50 can be stored and used at alater time.

Referring to FIG. 11, there is illustrated the internal components of anexemplary version of one of the IGs 42. As mentioned above, the IGs 42are used for interfacing the FPGA tile 20 to other FPGA tiles ordevices, or to pad rings for connecting the FPGA tile 20 to IC packagepins. The PI[0:9] bus is used to receive data from outside of the FPGAtile 20 and pass the data to the first set of routing conductors insideof the FPGA tile 20 via the CI[0:9] bus. The CO[0:9] bus is used toreceive data from the first set of routing conductors inside of the FPGAtile 20 and pass the data to outside of the FPGA tile 20 via the PO[0:9]bus.

Similar to the FG 40, the IG 42 also receives LINT signals via thesecond set of routing conductors. Specifically, for signals coming intothe FPGA tile 20, the PI[0:9] bus is coupled to ten, twelve-to-onemultiplexers 110 that select the signals which form the CI[0:9] bus. If,however, the first set of routing conductors that is coupled to theCI[0:9] bus is unable to route a signal to the desired location withinthe FPGA tile 20, the signal can be selected as the “bLINT” signal bythe twelve-to-one multiplexer 112. The bLINT signal is routed by thesame second set of routing conductors that is used to the route the LINTsignals generated by the FGs 40. As such, the bLINT signal can be routedalong this second set of routing conductors to any of the FGs 40 and/orIGs 42 in the FPGA tile 20. This provides a way to route any of theincoming signals PI[0:9] to any destination within the FPGA tile 20 evenif the first set of routing conductors carrying the CI[0:9] bus does notprovide a path to that destination.

Similarly, for signals leaving the FPGA tile 20, the CO[0:9] bus iscoupled to ten, twelve-to-one multiplexers 114 that select the signalswhich form the PO[0:9] bus. If, however, the first set of routingconductors that are coupled to the PO[0:9] bus are unable to route asignal to the desired location outside of the FPGA tile 20 (e.g., in aneighboring FPGA tile), the signal can be selected as the “tLINT” signalby the twelve-to-one multiplexer 116. The tLINT signal is routed by asecond set of routing conductors that is used to route the signals froma second output port LINT in the neighboring FPGA tile, and as such, thetLINT signal can be routed to any of the FGs and/or IGs in theneighboring FPGA tile. This provides a way to route any of the outgoingsignals CO[0:9] to any destination within the neighboring FPGA tile evenif the first set of routing conductors carrying the PO[0:9] bus does notprovide a path to that destination.

As mentioned above, the second set of routing conductors within the FPGAtile 20 that carries LINT signals includes the LGG[0:5] bus.Specifically, several LINT signals that need to be routed around theFPGA tile 20 are grouped together and travel via the LGG[0:5] bus. TheLGG[0:5] bus is provided to every FG 40 and IG 42 so that LINT signalscan be sent to every device. The IGs 42 receive the LGG[0:5] bus frominside of the FPGA tile 20 at input bLGG[0:5]. The bLGG[0:5] input iscoupled to the six-to-one multiplexers 118, 120, which have theiroutputs coupled to the multiplexers 114, 116. In this way, any LINTsignal generated within the FPGA tile 20 can be sent outside of the FPGAtile 20 on the PO[0:9] bus or as the tLINT signal by programming theappropriate multiplexers 114, 116 to select the outputs of theappropriate multiplexers 118, 120.

Similarly, an LGG bus in a neighboring FPGA tile can be connected to thetLGG[0:5] input of the IG 42. The tLGG[0:5] input is coupled to thesix-to-one multiplexers 122, 124, which have their outputs coupled tothe multiplexers 110, 112. In this way, any LINT signal generatedoutside of the FPGA tile 20 can be sent inside the FPGA tile 20 on theCI[0:9] bus or as the bLINT signal by programming the appropriatemultiplexers 110, 112 to select the outputs of the appropriatemultiplexers 122, 124.

It should be understood that in certain situations the tLINT signal andtLGG[0:5] bus may not be needed and can be eliminated from the IG 42 inaccordance with the present invention. This is illustrated in FIG. 12which shows an alternative IG 42′ having no tLINT or tLGG[0:5] inputs.An example of a situation where the tLINT signal and tLGG[0:5] bus arenot needed is where the IG 42′ is used to couple the FPGA tile 20 to apad ring, such as one of the pad rings 28, 30, 32, 34. In this scenariothe PO[0:9] outputs and the PI[0:9] inputs will be coupled through thepad ring to the IC package I/Os (i.e., the IC package input/outputpins). This is illustrated in the figure for the PI[0:9] bus in that thePI[0:9] bus is coupled to several I/Os 101, 103, 105, 107, 109. Therewill typically be no second set of routing conductors in the pad ringsto make use of the tLINT signal and tLGG[0:5] bus. The multiplexers 116,122, 124 are eliminated, and the multiplexers 110, 112 are replaced withten-to-one multiplexers 126, 128.

FIG. 12 also illustrates another important feature of the presentinvention. Specifically, in the scenario where a side of the FPGA tile20 is to be coupled to a pad ring for I/O purposes, the I/Os 101, 103,105, 107, 109 may be directly coupled to the IG 42′. Furthermore, theI/Os 101, 103, 105, 107, 109 may be directly coupled to the multiplexers126, 128. In other words, the I/Os 101, 103, 105, 107, 109 can bedirectly coupled to the multiplexers 126, 128 without first connectingto a routing channel. The connection to a routing channel is made afterthe IG 42′ and multiplexers 126, 128. Thus, in this scenario, I/Os aredirectly coupled to the multiplexers 126, 128 and then go on to therouting channel or other routing resources.

It should also be understood that the IGs of two neighboring FPGA tilesmay be combined into one IG in accordance with the present invention.For example, with the IG 42 shown in FIG. 11, the PO[0:9], PI[0:9],tLGG[0:5] buses and the tLINT output port will typically not be coupledto a separate IG of a neighboring tile, but rather, these input andoutput ports will be coupled into the routing structures of theneighboring FPGA tile and the IG 42 will also serve as the IG of theneighboring tile.

By way of example, any of the multiplexers (selection circuits)discussed herein, such as for example multiplexers 86, 88, 90, 92, 94,96, 98, 100, 102, 104, may comprise any of the selection circuitsdescribed in United States Publication Number US-2001-0011908-A1, thefull disclosure of which is hereby incorporated into the presentapplication by reference.

Referring to FIG. 13, there is illustrated a more detailed diagramshowing approximately one-quarter of an exemplary version of the FPGAtile 20. The portion of the FPGA tile 20 that is illustrated isdesignated by 129 in FIG. 5. It will be appreciated by those of ordinaryskill in the art that the remaining portions of the FPGA tile 20 aremirror images of the illustrated portion 129.

FIG. 13 illustrates the first set of routing conductors of the FPGA tile20 that is used to route signals via input and output ports 44 of theFGs 40. As discussed above, the input and output ports 44 carry thesignals to first input ports EUI[0:4], EBI[0:4], and the signals fromfirst output ports Y[0:4]. The first set of routing conductors of theFPGA tile 20 also handles routing of the CO[0:9] and CI[0:9] buses toand from the IGs 42.

The first set of routing conductors of the FPGA tile 20 includes firsthorizontal routing buses 150, 152, 154, 156 and several vertical regularrouting buses 158, 160, 162. By way of example, the horizontal routingbuses 150, 152, 154, 156 may each include X number of lines, thehorizontal routing bus 164 may include A number of lines, the verticalrouting buses 160, 162 may each include Y number of lines, and thevertical routing bus 158 may include B number of lines. By way offurther example, the horizontal routing buses 150, 152, 154, 156 mayeach include 50 lines, the horizontal routing bus 164 may include 70lines, the vertical routing buses 160, 162 may each include 60 lines,and the vertical routing bus 158 may include 70 lines.

In order to transfer data from one routing bus to another routing bus orto an FG 40 or an IG 42, several routing interconnect areas 130, 132,134, 136, 138, 140, 142, 144, 146, 148 are included in the FPGA tile 20.The routing interconnect areas 130, 138, 144, 146 are used to transferdata from one of the vertical routing buses to one of the horizontalrouting buses. The other routing interconnect areas 132, 134, 136, 140,142, 148 are used to transfer data to or from one of the IGs 42 or oneof the FGs 40 to or from one of the vertical routing buses or one of thehorizontal routing buses. In general, the routing buses and the routinginterconnect areas form the regular routing structure of the FPGA tile20.

FIG. 14 illustrates an exemplary structure for the routing interconnectareas 130, 132, 134. In this example, the horizontal routing bus 152includes 50 lines and the vertical routing bus 160 includes 60 lines. Itshould be well understood, however, that the specific number of lines inany of the routing buses may vary in accordance with the presentinvention. Furthermore, it should be well understood that the specificnumber of lines in any of the signal buses, such as for exampleEUI[0:4], EBI[0:4], Y[0:4], LGG[0:5], GG[0:7], JI[0:7], GI[0:1],CO[0:9], CI[0:9], PO[0:9], PI[0:9], may vary in accordance with thepresent invention.

Each of the routing interconnect areas 130, 132, 134 includes severaltransistor switches and corresponding memory cells which are used formaking the connections between the various buses. Each transistor switchand memory cell is illustrated in the figure as a circle (or bubble)drawn at the intersection of signal lines to be coupled together. Inorder to illustrate this, FIG. 15 shows a detail of the circlesdesignated by 170. The circles 172, 174, 176, 178, 180 includetransistor switches M2, M4, M6, M8, M10, respectively. Each of thetransistor switches M2, M4, M6, M8, M10 has its source and drain coupledto intersecting signal lines and its gate coupled to a correspondingmemory cell 182, 184, 186, 188, 190. Each of the memory cells stores onebit of configuration data to control whether or not its correspondingtransistor switch is turned on or off. When a transistor switch isturned on, the lines to which it is connected are coupled together.

Referring back to FIG. 14, the operation of the first set of routingconductors and the routing interconnect areas will be described infurther detail. One of the FGs 40 and its nearby routing interconnectareas 130, 132, 134 are illustrated. The Y[0:4] output port of the FG 40is coupled to the routing interconnect area 134, and the EBI[0:4] inputport of the FG 40 is coupled to the routing interconnect area 132. In atypical scenario, the FG 40 outputs data onto the Y[0:4] bus and therouting interconnect area 134 is used to transfer that data onto bus160. This is done by turning on the transistor switch inside theillustrated circle (or bubble) at the appropriate intersection of signallines. Each transistor switch is turned on by programming itscorresponding memory cell. Similarly, the routing interconnect area 132is used to transfer data from bus 152 onto the EBI[0:4] bus of the FG40. Again, this is accomplished by programming the memory cell to turnon the transistor switch at the appropriate intersection. The routinginterconnect area 130 is used to transfer data from bus 160 onto bus152, again by programming the memory cell to turn on the transistorswitch at the appropriate intersection.

As illustrated, the routing interconnect areas 130, 132, 134 includetransistor switches and memory cells at many intersections of signallines, but not at all intersections. (Again, the transistor switches andmemory cells are inside the illustrated circles or bubbles). When atransistor switch and memory cell is included at every intersection ofsignal lines, this is known as a “fully populated” routing interconnectportion. A fully populated routing interconnect portion is shown in therouting interconnect area 132 at 192. It should be well understood thatthe specific intersections chosen to have a transistor switch and memorycell, and which areas are fully populated (if any), may vary widely inaccordance with the present invention. In other words, many differentpatterns of transistor switches and memory cells may be used in therouting interconnect areas 130, 132, 134 in accordance with the presentinvention.

The other routing interconnect areas 136, 138, 140, 142, 144, 146, 148in the FPGA tile 20 are similar to the routing interconnect areas 130,132, 134. Some, however, will have different numbers of signal lines andintersections. For example, the routing interconnect areas 136, 144 mayhave a greater number of signal lines in the horizontal bus 164 due inpart to ten signals (instead of five) being transferred to the CO[0:9]bus of the IGs 42. Similarly, the routing interconnect areas 146, 148will have fewer inputs and/or outputs because they are located at theend of a row.

The number of transistor switches used and their positioning in the FPGAtile 20 can change in accordance with the present invention. Thespecific arrangement and positioning of IGs, FGs, routing buses, routinginterconnect areas, and switching transistors within routinginterconnect areas will vary greatly depending on the particularapplication. It should be understood that the configurations illustratedin the figures herein are example configurations.

FIGS. 16A and 16B illustrate the second set of routing conductors of theFPGA tile 20. As discussed above, the second set of routing conductorsis separate from the first set of routing conductors and routinginterconnect areas used to route the output signals Y[0:4]. The secondset of routing conductors is used for routing signals via input andoutput ports 46 which include input port LGG[0:5] and output port LINT.The LINT routing structure is a second set of routing conductors thatcan be used to send a signal in situations when the first set of routingconductors cannot be used to send a signal to the intended destination.This may occur because a transistor switch and memory cell may not havebeen placed at the needed intersection of signal lines in one or more ofthe first set of routing conductors regular routing interconnect areas130, 132, 134, 136, 138, 140, 142, 144, 146, 148. If the neededconnections cannot be made with the first set of routing conductorsinterconnect areas, the signal can be sent to any of the FGs 40 and/orIGs 42 by selecting the needed one of the output signals Y[0:4] as theLINT signal as described above and sending it over the second set ofrouting conductors.

The signals sent via the LINT output port of six devices, which can beany combination of FGs 40 and/or IGs 42, are assembled to form theLGG[0:5] bus. While the LGG[0:5] bus is illustrated as a six-signal bus,it should be well understood that the number of signals in the LGG busmay vary in accordance with the present invention. Furthermore, the LGGbus is made up of LINT signals from the FGs 40 and bLINT signals fromthe IGs 42. As discussed above, the “b” designation on the bLINT signalsof the IGs 42 indicates that these signals are internal to the FPGA tile20 as opposed to the external tLINT signals. Therefore, when discussingthe formation of the LGG[0:5] bus, use of the term “LINT” will generallybe intended to cover both the LINT signal generated by the FGs 40 andthe bLINT signal generated by the IGs 42.

The LGG[0:5] bus is assembled as follows. The first column of IGs 42 hastheir bLINT outputs coupled to an eight-signal bus 200. Six,eight-to-one multiplexers 202 are coupled to bus 200. The output of eachof the multiplexers 202 is coupled to a corresponding tri-state buffer204. The outputs of the tri-state buffers 204 are coupled to theLGG[0:5] bus. In the second column of FGs 40 and two IGs 42, the LINToutput of each FG 40 and the bLINT output of each IG 42 are coupled to aten-signal bus 206. Six, ten-to-one multiplexers 208 are coupled to bus206. The output of each of the multiplexers 208 is coupled to acorresponding tri-state buffer 204, which in turn are coupled to theLGG[0:5] bus.

In a similar manner, the last column of IGs 42 has their bLINT outputscoupled to an eight-signal bus 210. Six, eight-to-one multiplexers 202and tri-state buffers 204 couple bus 210 to the LGG[0:5] bus. In thesecond to last column of FGs 40 and two IGs 42, the LINT output of eachFG 40 and the bLINT output of each IG 42 are coupled to a ten-signal bus212, which in turn is coupled to the LGG[0:5] bus via six, ten-to-onemultiplexers 208 and tri-state buffers 204. It should be understood thatthe rest of the FGs 40 and IGs 42 in the FPGA tile 20 that are not shownin FIGS. 16A and 16B are connected to the LGG[0:5] bus in a similarmanner.

During operation, each of the multiplexers 202, 208 selects a LINTsignal from its input bus, that is, the respective one of buses 200,206, 210, 212. Up to six of these selected LINT signals may be placedonto the LGG[0:5] bus. This is done by placing six of the tri-statebuffers 204 into a conducting state and placing the remaining tri-statebuffers into a non-conducting state. The six tri-state buffers 204 thatare placed into a conducting state should correspond to the multiplexers202, 208 that have selected the desired LINT signals.

The LGG[0:5] bus is routed to all of the FGs 40 and IGs 42 in the FPGAtile 20. In this way, a LINT signal from any of the FGs 40 and IGs 42can be sent to any of the FGs 40 and IGs 42, independent of the firstset of routing conductors used for the Y[0:4] bus.

Referring back to FIGS. 16A and 16B, FIGS. 16A and 16B also show therouting of the GG[0:7] bus. As discussed above, the GG[0:7] bus formsthe inter-tile global signals 48. These signals are sent to every FG 40in all FPGA tiles. Thus, the GG[0:7] bus extends through the border ofthe FPGA tile 20 as indicated at 214 so that it can go to other FPGAtiles. The GG[0:7] bus extends through the border of the FPGA tile 20without going through an IG 42. As discussed above, selected ones of theinput signals GG[0:7] may be used to control theclock/enable/preset/clear (C/E/P/C) inputs of flip-flops included ineach FG 40. It should be understood that the GG[0:7] bus may includemore or fewer signals in accordance with the present invention.

Referring to FIG. 17, the global signal routing structure 36 isillustrated in more detail. As mentioned above, the global signalrouting structure 36 is used to route inter-tile global signals betweenthe FPGA tiles 20. For example, the GG[0:7] bus (which forms theinter-tile global signals 48) is included in the global signal routingstructure 36 and is shown connecting to all four FPGA tiles 20. TheGG[0:7] bus can be coupled to inputs 220, 222 to send signals that areto be sent on the GG[0:7] bus. Selected ones of the inputs 220, 222 canbe coupled to selected signals of the GG[0:7] bus by means of transistorswitches and memory cells (such as is described above), examples ofwhich are indicated by circles 224, 226.

As shown, the global signal routing structure 36 also includes bus 230to connect to the pad ring.

When two FPGA tiles 20 are coupled together, the IG outputs of one tileare typically coupled directly to the IG inputs of the other tile. Or,as discussed above, the IGs of the two tiles can be combined as one IG.FIG. 18 illustrates another option for coupling two FPGA tiles 20together. Specifically, an intermediate routing track 240 may be used.The output PO[0:9] bus of the IG 42 of one tile 20 is coupled to thetrack 240, and the input PI[0:9] bus of the IG 42 of the other tile 20is coupled to the track 240 at a different location. The connections tothe track 240, for example at points 242, 244, 246, may be by way ofhard wired connections for by way of transistor switches and memorycells as described above. The later would, of course, be programmable.It should be understood that the use of the intermediate routing track240 is optional.

FIG. 19 shows the LINT signal distribution through a fixed network. Asset forth above, The LINT signal is sent via a second set of routingconductors that can be used to send a signal in situations when thefirst set of routing conductors Y[0:4] cannot be used to send a signalto the intended destination. This may occur because a transistor switchand memory cell may not have been placed at the needed intersection ofsignal lines in one or more of the regular routing interconnect areas130, 132, 134, 136, 138, 140, 142, 144, 146, 148. If the neededconnections cannot be made with the first set of routing conductors, thesignal can be sent to any of the FGs 40 and/or IGs 42 by selecting theneeded one of the regular routing output signals Y[0:4] as the LINTsignal as described above and sending it over the second set of routingconductors.

FIGS. 20 and 21 show yet another embodiment of the present invention. Inthis embodiment a third routing structure is added to FPGA tile 20making FPGA tile 20 extremely flexible and enabling signals to be sentto or from any FG or IG 42. FIGS. 20 and 21 show the SLINT signaldistribution through a flexible network. The SLINT network is a thirdset of routing conductors that can be used to send a signal insituations when the first set of routing conductors 44 cannot be used tosend a signal to the intended destination. The SLINT network is anextension of the LINT concept except that the SLINT network employsflexible routing resources with tracks and switches. Every output of anFG 40 Y[0:4] can be used to drive the SLINT network. In addition, everyoutput of an IG 42 PI[0:9] can be used to drive the SLINT network. Asignal will be selectively placed in the SLINT network if the first setof routing conductors cannot be used to send a signal. This may occurbecause a transistor switch and memory cell may not have been placed atthe needed intersection of signal lines in one or more of the first setof routing conductors interconnect areas 130, 132, 134, 136, 138, 140,142, 144, 146, 148. Once in the SLINT network, signals travel through aspecial set of tracks, SLVT 248, SLHT 250 and SLIT 252 before reachingthe third input ports of FGs 40, namely SL[0:4] 254 via input track SLIT[0:4].

FIG. 21 illustrates an exemplary structure for the routing interconnectareas 256, 258, 260 and 262 between adjacent FGs. It should be wellunderstood, however, that the specific number of lines in any of therouting buses may vary in accordance with the present invention.Furthermore, from this disclosure, it will be apparent to persons ofordinary skill in the art that the specific number of lines in any ofthe signal buses, such as for example Y[0:4], SL[0:4], may vary inaccordance with the present invention.

As set forth above, each of the third set of routing conductorsinterconnect areas 256, 258, 260, 262 includes several transistorswitches and corresponding memory cells which are used for making theconnections between the various buses. Each transistor switch and memorycell is illustrated in the figure as a circle (or bubble) drawn at theintersection of signal lines to be coupled together. In order toillustrate this, FIG. 15 shows a detail of the circles designated by170.

As illustrated, the third set of routing conductors interconnect areas256, 258, 260, 262 includes transistor switches and memory cells at manyintersections of signal lines, but not at all intersections. (Again, thetransistor switches and memory cells are inside the illustrated circlesor bubbles). When a transistor switch and memory cell is included atevery intersection of signal lines, this is known as a “fully populated”routing interconnect portion. A fully populated routing interconnectportion is shown in the routing interconnect area 258. It should be wellunderstood that the specific intersections chosen to have a transistorswitch and memory cell, and which areas are fully populated (if any),may vary widely in accordance with the present invention. In otherwords, many different patterns of transistor switches and memory cellsmay be used in the routing interconnect areas 256, 258, 260, 262 inaccordance with the present invention.

The number of transistor switches used and their positioning in the FPGAtile 20 can change in accordance with the present invention. Thespecific arrangement and positioning of IGs, FGs, routing buses, routinginterconnect areas, and switching transistors within routinginterconnect areas will vary greatly depending on the particularapplication. From this disclosure, it will be apparent to persons ofordinary skill in the art that the configurations illustrated in thefigures herein are example configurations.

FIGS. 22 and 23 show the SLINT signal distribution through a flexiblenetwork as it pertains to IGs 42. FIGS. 22 and 23 illustrate anexemplary structure for the third set of routing conductors interconnectareas 264, 266, 268 and 270 between adjacent top/bottom IGs 42 andleft/right IGs 42. Every output of an IG 40, PI[0:9] can be used todrive the SLINT network.

As illustrated, the routing interconnect areas 264, 266, 268, 270includes transistor switches and memory cells at many intersections ofsignal lines, but not at all intersections. From this disclosure, itwill be apparent to persons of ordinary skill in the art, however, thatthe specific number of lines in any of the routing buses may vary inaccordance with the present invention. Furthermore, it should be wellunderstood that the specific number of lines in any of the signal buses,such as for example PI[0:9], SL[0:3], may vary in accordance with thepresent invention.

FIG. 24 discloses a method of routing a FPGA. A method of routing anFPGA in accordance with the present invention begins at input block 300.At input block 300, a user inputs a function netlist that defines a usercircuit. The user circuit will define the programmable connections to beprogrammed to implement the desired user function. These programmableconnections include programmable interconnections of the FPGA array, aswell as the connections within internal components included within theFPGA.

Internal components, as used in the present invention are defined as,for example, configurable functional groups, interface groups, selectioncircuits, multiplexer circuits, memory cells, look up tables, PLAblocks, non-volatile blocks, DRAM blocks, ROM blocks, RAM, FIFO, PLL,DLL, FLASH memory. multipliers, DSP cores, MPU cores, DAC, ADC, and anyother internal components as known by those skilled in the art.Programming the FPGA causes not only the programmable interconnectionsof the FPGA to be configured, but also causes the connections within theinternal components included within the FPGA to be connected whichultimately results in lines being coupled together or not being coupledtogether, due to transistors being turned on and off.

At step 302, the user circuit is optimized. Next at step 304, the usercells defining the optimized user circuit are placed in the FPGA. Atstep 306, the circuit is routed. Next, at step 308, it is determinedwhether the routing requirements of the user circuit are met using thefirst set of routing conductors. If the user circuit routingrequirements are not met using the first set of routing conductors, thethird set of routing conductors are engaged at step 310. The third setof routing conductors are employed in addition to the first set ofrouting conductors and are used only when the routing requirementscannot be met with first set of routing conductors.

Whether the user circuit routing requirements are met using the firstset of routing conductors or both the first and third set of routingconductors, at step 312 the bitstream is generated. Finally, at step314, the FPGA is programmed with the user circuit.

The full disclosures of the following United States Patent Applicationsare hereby incorporated into the present application by reference: U.S.patent application Ser. No. 09/231,998, filed Jan. 15, 1999, nowabandoned; U.S. patent application Ser. No. 09/281,008, filed Mar. 30,1999, now issued as U.S. Pat. No. 6,301,696; U.S. patent applicationSer. No. 09/285,563, filed Apr. 2, 1999, now issued as U.S. Pat. No.6,446,242; and U.S. patent application Ser. No. 09/318,198, filed May25, 1999, now issued as U.S. Pat. No. 6,211,697.

From this disclosure, it will be apparent to persons of ordinary skillin the art that various alternatives to the embodiments of the inventiondescribed herein may be employed in practicing the invention. It isintended that the following claims define the scope of the invention andthat structures and methods within the scope of these claims and theirequivalents be covered thereby.

1. (canceled)
 2. An apparatus including a field-programmable gate array(FPGA), the FPGA comprising: a first FPGA tile that includes: aplurality of functional groups (FGs) arranged in rows and columns, eachconfigurable to perform logic operations, each FG having a first,second, and third set of input ports and a first, second, and third setof output ports; a plurality of interface groups (IGs) surrounding theplurality of FGs such that one IG is positioned at each end of each rowand column; a primary routing structure comprising a first set ofrouting conductors disposed within said first FPGA tile programmablycoupled to said first set of output ports of said FGs, configured toreceive signals, route signals within said first FPGA tile, and providesaid signals to said first set of input ports of said FGs; a secondaryrouting structure comprising a second set of routing conductors thatare: disposed across said first FPGA tile independent of said firstrouting structure, coupled to said second set of output ports of saidFGs, configured to receive, select and route signals around said firstFPGA tile and within first FPGA tile, and provide said signals to saidsecond set of input ports of said FGs; and a tertiary routing structurecomprising a third set of routing conductors that are: disposed acrosssaid first FPGA tile independent of said first and second routingstructure, coupled to said third set of output ports of said FGs, andemploying a plurality of tracks and a plurality of switches to receivesignals, route signals around said first FPGA tile and within said firstFPGA tile, and provide said signals to said third set of input ports ofsaid FGs when said first set of routing conductors cannot be used. 3.The apparatus in accordance with claim 2, wherein each of the IGsfurther comprises: a plurality of output multiplexers configured toselect signals received from the first and second routing structures andprovide the selected signals to outside of the FPGA tile.
 4. Theapparatus in accordance with claim 2, wherein each of the IGs furthercomprises: a plurality of input multiplexers configured to selectsignals received from outside of the FPGA tile and provide the selectedsignals to the first and second routing structures inside of the FPGAtile.
 5. The apparatus in accordance with claim 4, wherein the apparatusfurther comprises: a plurality of input/output pads (I/Os) and each ofthe input multiplexers is coupled directly to at least one of the I/Os.6. The apparatus in accordance with claim 2, wherein the FPGA furthercomprises: a second FPGA tile that includes a plurality of FGs, aplurality of IGs, and a first, second, and third set of routingconductors arranged in a manner substantially similar to the first FPGAtile, wherein at least one IG of the first FPGA tile is coupled to atleast one IG of the second FPGA tile.
 7. The apparatus in accordancewith claim 6, wherein the FPGA further comprises: a third FPGA tile thatincludes a plurality of FGs, a plurality of IGs, and a first, second,and third set of routing conductors arranged in a manner substantiallysimilar to the first FPGA tile, wherein at least one IG of the firstFPGA tile is coupled to at least one IG of the third FPGA tile.
 8. Theapparatus in accordance with claim 2, wherein: the apparatus furthercomprises a system-on-a-chip (SOC).
 9. The apparatus in accordance withclaim 2, wherein each of the FGs further comprises: a multiplexerconfigured to select one of the primary output signals as an FGsecondary routing signal.
 10. The apparatus in accordance with claim 2,wherein: each of the IGs further comprises a first, second, and thirdinput port and a first, second, and third output port; the tertiaryrouting structure is coupled to and provides signals to the third inputports of at least one of the IGs; and the tertiary routing structure iscoupled to and receives signals from the third output port of at leastone of the IGs.
 11. The apparatus in accordance with claim 10, whereineach of the IGs further comprises: a multiplexer configured to select asignal received from outside of the FPGA tile as an IG tertiary routingsignal, wherein the tertiary routing structure is configured to selectand route the IG tertiary routing signal around the first FPGA tile. 12.The apparatus in accordance with claim 10, wherein each of the IGsfurther comprises: a multiplexer configured to select a signal receivedfrom the first routing structure, second routing structure, and thirdrouting structure, and transmit the signal outside the first FPGA tile.13. The apparatus in accordance with claim 2, wherein: said plurality oftracks intersect at a plurality of interconnect areas.
 14. The apparatusin accordance with claim 13 wherein: at least one of said plurality ofinterconnect areas is fully populated with said plurality of switches.15. The apparatus in accordance with claim 13 wherein: at least one ofsaid plurality of interconnect areas is not fully populated with saidplurality of switches.
 16. The apparatus in accordance with claim 2wherein: each of the plurality of switches comprises a transistor switchcoupled to and controlled by a memory cell.